🎓 Electrical Engineering, Universitas Tanjungpura (UNTAN)

Democratizing Edge AI & Grounded Semantic RAG

Building lightweight machine learning pipelines for resource-constrained hardware (<200KB model, <100KB RAM) alongside privacy-first local Retrieval-Augmented Generation architectures with verifiable citations and Schema.org Linked Data.

⚡ TinyML & Renewables

Inverter Fault Diagnosis

ESP32-S3 INT8 1D-CNN

📚 Privacy-First

Local Document RAG

~2GB RAM Footprint

🕸️ Semantic Web

Knowledge Graph Studio

Schema.org JSON-LD

Launch Interactive Lab Explore Projects Get in Touch

LIVE TELEMETRY: Inverter Waveform Monitor 50 Hz

Mode: Normal (Sinusoidal)

Frequency: 50.0 Hz

THD Sim: < 2.1%

Harmonic Noise: 0%

⚡ ESP32-S3 TinyML Pipeline: AC current is acquired and quantized to INT8 for real-time anomaly detection.

Open Source & Research

Featured Projects

System engineering architectures designed for computational efficiency, modularity, and scientific transparency.

Linked Data & Knowledge Graph v3.0.0 Released Apache-2.0

CorpusLD

Dual-Layer Academic Linked Data Engine & Deep Knowledge Graph Studio

An open-core extraction engine converting unstructured scientific papers, technical reports, and patents into Schema.org JSON-LD, W3C RDF Turtle, and Neo4j Cypher with live ROR, Wikidata, and Crossref authority linking.

Architecture	Dual-Layer (Layer 1: 4-Tier Ingestion & 5-Agent Map-Reduce \| Layer 2: Authority Resolvers & Multi-Format Graph Lake)
Parser Pipeline	4-Tier Fallback (PyPDF → LlamaParse → Unstructured → Stateful Cross-Page Table Stitcher)
Authority Resolvers	Live ROR v2 (Research Institutions) + Wikidata QID & MeSH URIs + Crossref & OpenAlex DOI Reconciliation
Unit Ontology	Universal Unit Ontology (Standardized parsing for SI, Biomedical, Energy, and Compound Units)
Semantic Exports	Schema.org JSON-LD, W3C RDF Turtle (.ttl), Neo4j Cypher (.cql), BibTeX (.bib), RIS (.ris), CSL-JSON, Google Scholar Meta
Security & QA	109 Passed Tests + SSRF Loopback Defense + Filename Path Traversal Protection + 100% Schema.org Validator Pass

Python 3.10+ FastAPI 3.0 W3C RDF Turtle Neo4j Cypher ROR v2 Registry Crossref / OpenAlex Qdrant Vector DB Schema.org JSON-LD

View GitHub Repository

Dual-Layer Architecture Map v3.0 Production

4-Tier Ingestion Header/Footer Stripper & Stitcher

↓

                        5-Agent Map-Reduce
                        Universal Unit Ontology
                      

↓

Live Authority Linkers ROR v2 • Crossref • Wikidata

↓

Multi-Format Graph Lake JSON-LD • Turtle • Cypher • BibTeX

Privacy-First Local RAG Active Development MIT License

Notebook-LocalLM-Studio

Edge-Optimized & Self-Reflective Local RAG for Multi-Document Intelligence

An enterprise-grade, offline Retrieval-Augmented Generation workspace engineered to process, synthesize, and answer queries across multiple PDF documents locally within a strict ~2GB RAM target.

SLM Core	Qwen 2.5 1.5B Instruct (Q5_K_M Quantization ~1.2GB) via Ollama
Embedding Engine	paraphrase-multilingual-MiniLM-L12-v2 (384-dim dense vectors)
Hybrid Re-Search	Deterministic heuristic table evaluator → Secondary Targeted Query
Citation Guardrails	Strict multi-document evidence citations [Doc.pdf \| Page X] preventing hallucinations

Python Streamlit Qdrant Ollama Qwen 2.5 1.5B MiniLM-L12-v2 pypdf

View GitHub Repository

Target Memory Footprint (~2GB RAM) Zero OOM

Model 1.2GB

DB 250MB

App 350MB

Free

Qwen 2.5 1.5B Q5_K_M (~1.2GB)

Qdrant Local Vector Client (~250MB)

Multilingual Embedding & Buffer (~350MB)

System Headroom (~200MB)

TinyML & Edge Hardware Thesis Project MIT License

Lightweight 1D-CNN Edge AI for Inverter Fault Diagnosis

Real-time Open-Circuit Fault Detection on ESP32-S3 for Solar PV Inverters

An embedded fault diagnosis system for single-phase full-bridge inverters powered by a lightweight 1D-CNN running directly on the ESP32-S3 without cloud or GPU dependencies.

🔬 Research Stage & Scientific Transparency:

End-to-end pipeline (acquisition → training → INT8 quantization → TFLite Micro → ESP32-S3) is validated. Physical hardware testbed dataset acquisition is the next scheduled milestone.

Model Size (INT8)	21.5 KB quantized (<15k params, TFLite Micro)
Input Window & Classes	128 samples / window • 6 Fault Classes (S1-S4 + Multi)
RAM Footprint	< 100 KB RAM Tensor Arena on ESP32-S3
Inference Latency	~8.4 ms on 240 MHz Xtensa LX7 dual-core

ESP32-S3 TensorFlow TFLite Micro INT8 Quantization C / C++ Thinger.io IoT

View GitHub Repository

Deployment Topology TFLite Micro

☀️ PV Inverter Full-Bridge AC

→ [Current Sensor] →

📟 ESP32-S3 1D-CNN INT8 Core

→ [WiFi / Telemetry] →

📊 Monitoring Thinger.io Dashboard

Model Size < 200 KB

RAM Usage < 100 KB

Target Savings ~85% Cheaper

Hands-On System Simulation

Interactive Engineering Lab

Directly test multi-agent RAG pipelines, schema generation, and real-time edge inverter fault detection in your browser.

CorpusLD v3.0 Dual-Layer Semantic Engine : Multi-Agent & Authority Simulator Agent State Machine : Active

Agent 1: Cover & Metadata Extractor Execution: 0.003s

/* Loading Agent Output... */

✓ Semantic Standards: 100% Passed (W3C RDF, Schema.org 109 Tests, Google Rich Results & Neo4j Ready)

Notebook-LocalLM-Studio : 2-Pass Hybrid Retrieval Simulator Engine: Qdrant Local + Qwen 2.5 1.5B

Choose Sample Research Query:

Pass 1: Semantic MiniLM Embedding 384-dim dense vector search on Qdrant collection

Heuristic Table & Metric Evaluator Tabular requirement detected: TRUE → Trigger Pass 2

Pass 2: Fast Re-Search Query Targeted retrieval on structured LlamaParse table chunks

Synthesis with Strict Citations Qwen 2.5 1.5B inference bound to page-level citations

Model Response (Grounded Evidence Response): Zero Hallucination Guardrail

Based on empirical benchmark data, inverter efficiency at 80% load reaches 97.2% with a Total Harmonic Distortion (THD) of 1.85% at 50 Hz fundamental frequency [Inverter_Test_Report.pdf | Page 14].

Extracted Tabular Evidence (Pass 2 LlamaParse):

Load (%)	Efficiency (%)	THD Current (%)	Loss (W)
50%	96.4%	2.40%	18.2 W
80%	97.2%	1.85%	22.4 W
100%	96.8%	2.10%	32.0 W

Core Competencies

Technical Radar & Stack

Practical, battle-tested expertise across embedded TinyML, vector retrieval systems, and semantic web engineering.

⚡

Embedded & TinyML

Edge Intelligence & IoT

ESP32-S3 Microcontroller Advanced
TFLite Micro & INT8 Quantization Advanced
1D-CNN Signal Processing Core Focus
C / C++ Embedded & Arduino Proficient
Thinger.io Cloud Telemetry Proficient

🧠

Neural RAG & SLM

Small Language Models & Vectors

Qdrant Vector Database Advanced
Ollama Offline SLM Inference Advanced
Qwen 2.5 / MiniLM Embedding Advanced
Multi-Agent RAG Orchestration Architect
Stateful Table Stitching Proprietary

🕸️

Semantic Web & API

Knowledge Graphs & Systems

Schema.org & JSON-LD Expert 100%
Python 3.10+ & FastAPI Advanced
Streamlit Interactive UI Advanced
TypeScript / JavaScript Intermediate
LlamaParse & Unstructured Proficient

⚙️

Tooling & Research

Workflows & Benchmarking

Git & GitHub Version Control Daily Driver
Docker & Containerization Working
VS Code / Linux CLI Advanced
Scientific Writing & IEEE Format Academic
PyTest & RAGAS Framework Roadmap

Timeline & Execution

Research Roadmap 2026 - 2027

Structured roadmap covering undergraduate thesis execution, scientific publication, and open-source productionization.

Phase 1

Q1 - Q3 2026

Architecture & End-to-End Pipeline Validation

Completed 1D-CNN INT8 pipeline for ESP32-S3, released CorpusLD v3.0.0 with Dual-Layer Knowledge Graph and live ROR authority linking, and built Notebook-LocalLM-Studio sub-2GB RAM workspace.

✓ CorpusLD v3.0 (Released) ✓ INT8 TFLite Micro Pipeline ✓ 2-Pass Retrieval Engine

Phase 2

Q4 2026 : Current Focus

Thesis Completion & Physical Dataset Acquisition

Physical Open-Circuit Fault dataset acquisition on laboratory hardware testbed / physical circuit simulations, robustness validation, and scientific paper submission.

• Hardware Testbed Acquisition • Scientific Paper Finalization

Phase 3

2027 : Planned

GraphRAG Productionization & Journal Integrations

Institutional Journal OJS plugins, enterprise Neo4j GraphRAG integration, automated benchmarking with RAGAS evaluation harness, and PyPI distribution maintenance.

• OJS Journal Plugins • Neo4j GraphRAG Integration • Docker CI/CD

Interactive Terminal

Developer Console & CLI

Type interactive shell commands to explore projects, trigger system simulators, or inspect live linked data.

sharriffajar@untan-edge-lab: ~ (bash / web-cli) Type help for available commands

INFO: Type help to view available commands.

Get in Touch

Collaboration & Contact

Open to research collaborations, open-source initiatives, TinyML implementations, or AI engineering opportunities.

📧

Direct Email sharrifff880@gmail.com

Open Email Client

🐙

GitHub Profile github.com/sharriffajar

Visit GitHub

💼

LinkedIn Profile linkedin.com/in/sharriffajar

Connect on LinkedIn

🏛️

Academic Affiliation Universitas Tanjungpura (UNTAN), Pontianak, Indonesia

UNTAN Website

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Democratizing Edge AI & Grounded Semantic RAG

Featured Projects

CorpusLD

Notebook-LocalLM-Studio

Lightweight 1D-CNN Edge AI for Inverter Fault Diagnosis

Interactive Engineering Lab

Test Signal Parameters (Single-Phase Full Bridge)

Edge 1D-CNN Classification Output (6-Class Softmax)

Technical Radar & Stack

Embedded & TinyML

Neural RAG & SLM

Semantic Web & API

Tooling & Research

Research Roadmap 2026 - 2027

Architecture & End-to-End Pipeline Validation

Thesis Completion & Physical Dataset Acquisition

GraphRAG Productionization & Journal Integrations

Developer Console & CLI

Collaboration & Contact

Send a Message